AXU15EG Base Board

AXU15EG Base Board is a carrier board from Alinx.

• MPN: AXU15EG-Carrier
• Type: carrier board
• Vendor: Alinx
• Status: active
• Product page: https://www.en.alinx.com/Product/SoC-Development-Boards/Zynq-UltraScale-plus-MPSoC/AXU15EGB.html
• Catalog page: https://boards.fpgadeveloper.com/carriers/AXU15EG-Carrier
• Structured data (JSON): https://boards.fpgadeveloper.com/data/carriers.json

Specifications

• Sensors:
• Type: temperature; Part: LM75
• M.2:
• Key: M-key; Direction: socket
• Interfaces:
• PCIe
• Video:
• Displayport: 1
• Mipi Csi: 1
• Networking:
• SFP Plus: 2
• Ethernet:
• Speed: 1000; Ports: 2
• Serial:
• Can: 2
• Rs485: 2
• USB:
• Connector: Type-A; Speed: 3.0; Role: host; Ports: 2
• Connector: Type-A; Speed: 2.0; Role: host; Ports: 2
• USB Bridge:
• Connector: Micro-B; Ports: 2
• Functions:
• uart
• Expansion:
• GPIO Header: 1
• FMC:
• Slot: HPC; Type: hpc; Vadj Min: 1.8; Vadj Max: 1.8
• Storage:
• Microsd: 1
• User I/O:
• Leds: 1
• Pushbuttons: 2
• Features:
• Battery Backed Rtc: Yes

Compatibility

Compatible FMC cards

• 2x QSFP28 FMC (OP120) — compatible, slot HPC, mechanical
• Ethernet FMC 1.8V (OP031-1V8) — compatible, slot HPC, mechanical
• Ethernet FMC Max (OP080) — compatible, slot HPC, mechanical
• FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot HPC, mechanical
• FPGA Drive FMC Gen4 (OP063) — compatible, slot HPC, mechanical
• M.2 M-key Stack FMC (OP073) — compatible, slot HPC, mechanical
• MCIO PCIe FMC (OP103) — compatible, slot HPC, mechanical
• Quad SFP28 FMC (OP081) — compatible, slot HPC, mechanical
• Robust Ethernet FMC 1.8V (OP041-1V8) — compatible, slot HPC, mechanical
• FMC SpaceWire/SpaceFibre Board Mk3 (FMC-SpaceWire-SpaceFibre-Mk3) — partial, slot HPC, mechanical

Used in kits

• AXU15EG (AXU15EG)

Notes

The FMC user I/O (36 differential pairs) routes to SoM banks 66/67, whose VCCO is supplied by the carrier's fixed +1.8 V rail (shared with Ethernet and USB 2.0; user guide Parts 3.12 and 3.20). No jumper or programmable VADJ selection mechanism is documented, so VADJ is fixed at 1.8 V.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*