ADRV1CRR-FMC
ADRV1CRR-FMC is a carrier board from Analog Devices.
- MPN: ADRV1CRR-FMC
- Type: carrier board
- Vendor: Analog Devices
- Status: active
- Product page: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adrv1crr-fmc.html
- Catalog page: https://boards.fpgadeveloper.com/carriers/ADRV1CRR-FMC
- Structured data (JSON): https://boards.fpgadeveloper.com/data/carriers.json
Specifications
- PCIe:
- Type: Edge; Gen: 2; Lanes: 1
- Networking:
- SFP Plus: 1
- Ethernet:
- Speed: 1000; Ports: 2
- Video:
- HDMI Out: 1
- Expansion:
- Pmod: 3
- FMC:
- Slot: FMC; Type: lpc; Vadj Min: 1.8; Vadj Max: 3.3
- Storage:
- Microsd: 1
- USB:
- Connector: Type-A; Speed: 2.0; Role: host; Ports: 2
- USB Bridge:
- Connector: Micro-B
- Functions:
- uart
- User I/O:
- Leds: 4
- Pushbuttons: 4
Compatibility
Compatible FMC cards
- Ethernet FMC 1.8V (OP031-1V8) — compatible, slot FMC, mechanical
- Ethernet FMC 2.5V (OP031-2V5) — compatible, slot FMC, mechanical
- FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot FMC, mechanical
- Robust Ethernet FMC 1.8V (OP041-1V8) — compatible, slot FMC, mechanical
- Robust Ethernet FMC 2.5V (OP041-2V5) — compatible, slot FMC, mechanical
- 2x QSFP28 FMC (OP120) — partial, slot FMC, mechanical
- Ethernet FMC Max (OP080) — partial, slot FMC, mechanical
- FMC SpaceWire/SpaceFibre Board Mk3 (FMC-SpaceWire-SpaceFibre-Mk3) — partial, slot FMC, mechanical
- FPGA Drive FMC Gen4 (OP063) — partial, slot FMC, mechanical
- M.2 M-key Stack FMC (OP073) — partial, slot FMC, mechanical
- Quad SFP28 FMC (OP081) — partial, slot FMC, mechanical
Notes
The ADRV1CRR-FMC is the FMC carrier for Analog Devices' SDR System-on-Module family. Compatible SoMs: ADRV9361-Z7035 (full functionality) and ADRV9364-Z7020 (subset — HDMI Out, Camera, PMOD0, SFP+, LEDs 1-3, slide switches, push-button 0 and the FMC connector are not supported on the Z7020 due to its smaller pin count). The ADRV9009-ZU11EG uses a different carrier (ADRV2CRR-FMC).
The four GTX serial transceivers from the mated SoM are allocated as:
| Lane | Destination |
|---|
| 1 | PCIe Gen2 x1 card-edge connector |
| 2 | FMC LPC connector |
| 3 | SFP+ cage |
| 4 | General-purpose SMA break-out |
The carrier has no FPGA of its own; all programmable logic is provided by the mated SoM. The Pmod tally (3) covers PMOD0, PMOD1 and PMOD_MIO from the wiki user guide — PMOD_MIO is wired to Zynq PS MIO pins rather than the PL.
FMC VADJ supports 1.8 V / 2.5 V / 3.3 V (discrete values; default 1.8 V), selected before power-on by 3-pin header P8 in the ADP5052 regulator's feedback network: open = 1.8 V (default), short 1-2 = 2.5 V, short 2-3 = 3.3 V. The FMC card's IPMI EEPROM is not consulted. The same VADJ rail also feeds the mated SoM's PL bank that drives the FMC LA signals.
--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*