ZedBoard
ZedBoard is an FPGA development board from Avnet, built around the XC7Z020-1CLG484C.
- MPN: ZedBoard
- Type: FPGA development board
- Vendor: Avnet
- Device: XC7Z020-1CLG484C
- Status: active
- Price: 499 USD
- Product page: https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/zedboard/
- Catalog page: https://boards.fpgadeveloper.com/boards/ZedBoard
- Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json
Specifications
- Memory:
- Type: DDR3; Size Mb: 512
- Flash:
- Type: QSPI; Size Mb: 32
- Audio:
- Codec: ADAU1761
- Line In: 1
- Line Out: 1
- Headphone Jack: 1
- Microphone: 1
- Video:
- HDMI Out: 1
- Vga Out: 1
- Display:
- Oled: 128x32
- Networking:
- Ethernet:
- Speed: 1000; Ports: 1
- USB:
- Connector: Micro-B; Speed: 2.0; Role: otg
- USB Bridge:
- Connector: Micro-B
- Functions:
- jtag
- uart
- Expansion:
- Pmod: 5
- Xadc Header: 1
- FMC:
- Slot: LPC; Type: lpc
- Storage:
- SD: 1
- User I/O:
- Leds: 9
- Pushbuttons: 7
- Dip Switches: 8
Device Attributes
Resources
- LUTs: 53,200
- Flip-Flops: 106,400
- Block RAM (36Kb): 140
- DSP Slices: 220
- MMCMs: 4
- HR I/O Pins: 200
Vivado
- Tool Part: xc7z020clg484-1
- ML Standard Support: Yes
Compatibility
Compatible FMC cards
- Ethernet FMC 2.5V (OP031-2V5) — compatible, slot LPC, verified
- Robust Ethernet FMC 2.5V (OP041-2V5) — compatible, slot LPC, verified
- Ethernet FMC 1.8V (OP031-1V8) — compatible, slot LPC, mechanical
- FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot LPC, mechanical
- RPi Camera FMC (OP068) — compatible, slot LPC, mechanical
- Robust Ethernet FMC 1.8V (OP041-1V8) — compatible, slot LPC, mechanical
Notes
Configuration
Boot mode is determined by jumper headers labelled MIO2-MIO6.
| Boot mode | MIO6 | MIO5 | MIO4 | MIO3 | MIO2 |
|---|
| JTAG (cascaded) | X | 0 | 0 | 0 | 0 |
| JTAG (independent) | X | 0 | 0 | 0 | 1 |
| Quad-SPI | X | 1 | 0 | 0 | X |
| SD Card | X | 1 | 1 | 0 | X |
Notes:
* 0 = install jumper between middle pin and GND * 1 = install jumper between middle pin and 3V3 * X = don't care * MIO6 determines PLL used (0) or bypassed (1)
--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*