VPK120

VPK120 is an FPGA development board from AMD Xilinx, built around the XCVP1202-2MSEVSVA2785.

• MPN: VPK120
• Type: FPGA development board
• Vendor: AMD Xilinx
• Device: XCVP1202-2MSEVSVA2785
• Status: active
• Price: 11994 USD
• Product page: https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/vpk120.html
• Catalog page: https://boards.fpgadeveloper.com/boards/VPK120
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: LPDDR4; Size Mb: 12288
• Clocking:
• Programmable: Yes
• PCIe:
• Type: Edge; Gen: 5; Lanes: 8
• Type: Edge; Gen: 4; Lanes: 16
• Networking:
• QSFP Dd: 2
• Ethernet:
• Speed: 1000; Ports: 2
• USB Bridge:
• Connector: Micro-B
• Functions:
• jtag
• Connector: Type-A
• Functions:
• uart
• Expansion:
• FMC:
• Slot: FMCP; Type: fmcp; Vadj Min: 1.2; Vadj Max: 1.5
• Storage:
• Microsd: 1
• User I/O:
• Leds: 4
• Pushbuttons: 7
• Dip Switches: 4
• Features:
• Power Monitoring: Yes
• Programmable Vadj: Yes

Device Attributes

Resources

• LUTs: 900,224
• Flip-Flops: 1,800,448
• Block RAM (36Kb): 1,341
• UltraRAM: 677
• DSP Slices: 3,984
• MMCMs: 13
• XPIO Pins: 703
• Transceivers: 20 (GTM, 112.0 Gb/s max)
• Transceivers: 12 (GTYP, 32.75 Gb/s max)

Vivado

• Tool Part: xcvp1202-vsva2785-2ms-e
• ML Standard Support: No

Compatibility

Compatible FMC cards

• 2x QSFP28 FMC (OP120) — compatible, slot FMCP, verified
• Ethernet FMC Max (OP080) — compatible, slot FMCP, verified
• FPGA Drive FMC Gen4 (OP063) — compatible, slot FMCP, verified
• M.2 M-key Stack FMC (OP073) — compatible, slot FMCP, verified
• MCIO PCIe FMC (OP103) — compatible, slot FMCP, verified
• Quad SFP28 FMC (OP081) — compatible, slot FMCP, verified
• FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot FMCP, mechanical
• RPi Camera FMC (OP068) — compatible, slot FMCP, mechanical

Notes

VADJ_FMC supports 1.2 V / 1.5 V (discrete values; default 1.5 V, board ships with VADJ_FMC set to 1.5 V). Set at boot by the ZU4 (XCZU4EG) System Controller, which reads the FMC's IPMI EEPROM to pick a voltage supported by both board and module; the rail is set to 0 V if no valid IPMI data is found. The system controller user interface allows the IPMI routine to be overridden with an explicit value.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*