VC709
VC709 is an FPGA development board from AMD Xilinx, built around the XC7VX690T-2FFG1761C.
- MPN: VC709
- Type: FPGA development board
- Vendor: AMD Xilinx
- Device: XC7VX690T-2FFG1761C
- Status: active
- Price: 8094 USD
- Product page: https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/dk-v7-vc709-g.html
- Catalog page: https://boards.fpgadeveloper.com/boards/VC709
- Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json
Specifications
- Memory:
- Type: DDR3; Size Mb: 4096; Form Factor: sodimm
- Type: DDR3; Size Mb: 4096; Form Factor: sodimm
- Flash:
- Type: BPI; Size Mb: 32; Width Bits: 16
- Clocking:
- Programmable: Yes
- Sma Clock In: 4
- PCIe:
- Type: Edge; Gen: 3; Lanes: 8
- Networking:
- SFP Plus: 4
- USB Bridge:
- Connector: Micro-B
- Functions:
- jtag
- Connector: Mini-B
- Functions:
- uart
- Expansion:
- Xadc Header: 1
- FMC:
- Slot: HPC; Type: hpc; Vadj Min: 1.8; Vadj Max: 1.8
- User I/O:
- Leds: 8
- Pushbuttons: 5
- Dip Switches: 8
- Features:
- Power Monitoring: Yes
Device Attributes
Resources
- LUTs: 433,200
- Flip-Flops: 866,400
- Block RAM (36Kb): 1,470
- DSP Slices: 3,600
- MMCMs: 20
- HP I/O Pins: 850
- Transceivers: 36 (GTH, 13.1 Gb/s max)
Vivado
- Tool Part: xc7vx690tffg1761-2
- ML Standard Support: No
Compatibility
Compatible FMC cards
- Ethernet FMC 1.8V (OP031-1V8) — compatible, slot HPC, verified
- Ethernet FMC Max (OP080) — compatible, slot HPC, verified
- FPGA Drive FMC Gen4 (OP063) — compatible, slot HPC, verified
- M.2 M-key Stack FMC (OP073) — compatible, slot HPC, verified
- MCIO PCIe FMC (OP103) — compatible, slot HPC, verified
- Quad SFP28 FMC (OP081) — compatible, slot HPC, verified
- Robust Ethernet FMC 1.8V (OP041-1V8) — compatible, slot HPC, verified
- 2x QSFP28 FMC (OP120) — compatible, slot HPC, mechanical
- FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot HPC, mechanical
- FMC SpaceWire/SpaceFibre Board Mk3 (FMC-SpaceWire-SpaceFibre-Mk3) — partial, slot HPC, mechanical
Notes
Configuration
FPGA configuration is determined by DIP switch SW11.
| Config mode | 1 | 2 | 3 | 4 | 5 |
|---|
| Master BPI | Note 4 | Note 4 | 0 | 1 | 0 |
| JTAG (independent) | X | X | 1 | 0 | 1 |
Notes:
1. X = don't care 2. 0 = OFF position 3. 1 = ON position 4. Switches 1 and 2 are A25 and A24 respectively and determine which of 4 bitstreams is booted from the Linear BPI flash
--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*