STEMlab 125-14 PRO Z7020 Gen 2

STEMlab 125-14 PRO Z7020 Gen 2 is an FPGA development board from Red Pitaya, built around the XC7Z020-1CLG400C.

• MPN: STEMlab-125-14-PRO-Z7020-Gen-2
• Type: FPGA development board
• Vendor: Red Pitaya
• Device: XC7Z020-1CLG400C
• Status: active
• Price: 889 EUR
• Product page: https://redpitaya.com/product/stemlab-125-14-pro-z7020-gen-2-oem/
• Catalog page: https://boards.fpgadeveloper.com/boards/STEMlab-125-14-PRO-Z7020-Gen-2
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR3; Size Mb: 1024; Width Bits: 32
• Analog:
• Role: adc; Part: LTC2145-14; Channels: 2; Resolution Bits: 14; Sample Rate Msps: 125
• Role: dac; Part: AD9767; Channels: 2; Resolution Bits: 14; Sample Rate Msps: 125
• Networking:
• Ethernet:
• Speed: 1000; Ports: 1
• USB:
• Connector: Type-C; Speed: 2.0; Role: host
• USB Bridge:
• Connector: Type-C
• Functions:
• uart
• Storage:
• Microsd: 1
• User I/O:
• Leds: 8

Device Attributes

Resources

• LUTs: 53,200
• Flip-Flops: 106,400
• Block RAM (36Kb): 140
• DSP Slices: 220
• MMCMs: 4
• HR I/O Pins: 125

Vivado

• Tool Part: xc7z020clg400-1
• ML Standard Support: Yes

Notes

• S1/S2 are not USB ports: the USB-C daisy-chain connectors are DC-coupled FPGA links that do not follow the USB-C specification. Only connect them to another Red Pitaya S1/S2 connector; use the HOST USB-C port for peripherals.
• E3 bank voltage: the E3 fast differential pairs (DIO11-DIO18) sit on Zynq bank 13, powered at 2.5V by default, and are not 3.3V tolerant. Bank 13 can be moved to 3.3V by relocating ferrite bead FB26 to FB25, which also changes the level of DIO8-DIO10 on E1.
• Boot source: SDIO_SEL (E3 pin 6) selects the boot device before power-on — low (default) boots from the microSD card, high boots from QSPI/eMMC on an E3 add-on module. With the QSPI eMMC module fitted the board does not power up automatically; press P-ON on the module.
• External clock: E2 pin 21 (CLK_SEL) high or unconnected selects the on-board 125MHz oscillator; tie it to GND to use Ext. ADC Clk± (E2 pins 23/24). This input drives the ADC/DAC/FPGA sampling clock directly — it is not a PLL reference, and changing its frequency at runtime requires an FPGA reset. Without a valid external clock the FPGA does not run (OS older than 2.07-48 fails to boot).
• Power supply: use a 5V/3A USB-C supply with functional CC lines. A 2-wire 5V supply works via the E2 +5V pin, or through USB-C with jumper JP5 bridged; in both cases the Power Error LED lighting is expected.
• Slow analog input range: the E2 auxiliary analog inputs have an actual full-scale range of 0-7.0V, not the 0-3.5V quoted in older specifications.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*