SIGNALlab 250-12

SIGNALlab 250-12 is an FPGA development board from Red Pitaya, built around the XC7Z020-3CLG400E.

• MPN: SIGNALlab-250-12
• Type: FPGA development board
• Vendor: Red Pitaya
• Device: XC7Z020-3CLG400E
• Status: active
• Price: 1751 EUR
• Product page: https://redpitaya.com/signallab-250-12/
• Catalog page: https://boards.fpgadeveloper.com/boards/SIGNALlab-250-12
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR3; Size Mb: 1024; Width Bits: 32
• Analog:
• Role: adc; Part: AD9613; Channels: 2; Resolution Bits: 12; Sample Rate Msps: 250
• Role: dac; Part: AD9746; Channels: 2; Resolution Bits: 14; Sample Rate Msps: 250
• Clocking:
• Programmable: Yes
• Sma Clock In: 1
• Networking:
• Ethernet:
• Speed: 1000; Ports: 1
• USB:
• Connector: Type-A; Speed: 2.0; Role: host; Ports: 2
• Connector: Header; Speed: 2.0; Role: host
• USB Bridge:
• Connector: Type-C
• Functions:
• uart
• Storage:
• Microsd: 1
• User I/O:
• Leds: 10

Device Attributes

Resources

• LUTs: 53,200
• Flip-Flops: 106,400
• Block RAM (36Kb): 140
• DSP Slices: 220
• MMCMs: 4
• HR I/O Pins: 125

Vivado

• Tool Part: xc7z020clg400-3
• ML Standard Support: Yes

Notes

• UART TX on E2 at power-up: PS_MIO8 (UART TX, E2 pin 7) is output-only and must be grounded or left floating at power-up — an external device driving it high during boot can stop the board from booting. Buffer it (e.g. open-drain buffer with pull-up) when designing extension hardware.
• S1/S2 daisy-chain connectors: these eSATA-style connectors carry 1.8V FPGA I/O and are not compatible with SATA storage devices. Unlike the STEMlab 125-14, the shared clock does not reach the ADC/DAC, so multi-board synchronisation uses the 10MHz SMA reference input plus the BNC trigger instead.
• Slow analog input range: the E2 auxiliary analog inputs (AI0-AI3) have an actual full-scale range of 0-7.0V, not the 0-3.5V quoted in older specifications.
• Enclosure: the aluminium housing must be removed to reach the E1/E2 extension connectors.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*