Agilex 5 E-Series 065B Modular

Agilex 5 E-Series 065B Modular is an FPGA development board from Altera, built around the A5ED065BB32AE4S.

MPN: MK-A5E065BB32AEA
Type: FPGA development board
Vendor: Altera
Device: A5ED065BB32AE4S
Status: active
Price: 1995 USD
Product page: https://www.altera.com/products/devkit/po-3274/agilex-5-fpga-and-soc-e-series-065b-modular-development-kit
Catalog page: https://boards.fpgadeveloper.com/boards/MK-A5E065BB32AEA
Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

Memory:
Type: DDR4; Size Mb: 8192; Width Bits: 32
Type: DDR4; Size Mb: 8192; Width Bits: 40; Ecc: Yes
Type: DDR4; Size Mb: 8192; Width Bits: 40; Ecc: Yes
Flash:
Type: QSPI; Size Mb: 256
Networking:
Sfp28: 1
Ethernet:
Speed: 2500; Ports: 2
PCIe:
Type: Edge; Gen: 4; Lanes: 4
Video:
HDMI In: 1
HDMI Out: 1
Displayport: 2
Sdi In: 1
Sdi Out: 1
Mipi Csi: 2
Expansion:
GPIO Header: 2
FMC:
Slot: J7; Type: fmcp; Vadj Min: 1.2; Vadj Max: 1.2
Storage:
Microsd: 1
USB Bridge:
Connector: Micro-B
Functions:
jtag
User I/O:
Leds: 4
Pushbuttons: 4
Dip Switches: 4
Clocking:
Programmable: Yes
Sma Clock In: 2
Sma Clock Out: 2
Features:
Power Monitoring: Yes

Compatibility

Compatible FMC cards

2x QSFP28 FMC (OP120) — compatible, slot J7, mechanical
Ethernet FMC Max (OP080) — compatible, slot J7, mechanical
FPGA Drive FMC Gen4 (OP063) — compatible, slot J7, mechanical
M.2 M-key Stack FMC (OP073) — compatible, slot J7, mechanical
MCIO PCIe FMC (OP103) — compatible, slot J7, mechanical
Quad SFP28 FMC (OP081) — compatible, slot J7, mechanical

Notes

Transceiver bank map

Bank	Use
UX 1A	FMC+ XCVR lanes 4-7 (17 Gbps max) and GBTCLK1_M2C
UX 1B	FMC+ XCVR lanes 0-3 (17 Gbps max) and GBTCLK0_M2C
UX 1C	UX0/UX1 2.5G TSN Ethernet, UX2 USB 3.1, UX3 SFP28 (10G)
UX 4A	DisplayPort 2.0
UX 4B	HDMI 2.0
UX 4C	PCIe Gen4 x4 (x16 edge connector)

Each FMC quad carries its own mezzanine reference clock: bank 1B takes GBTCLK0_M2C from J7.D4/D5, bank 1A takes GBTCLK1_M2C from J7.B20/B21.

CvP (Configuration via Protocol) is not supported. CvP needs a PCIe link on banks 1A/1B/1C, and none of those are wired to the PCIe edge connector. The FMC+ interface on banks 1A/1B is not compatible with the FMC+ to PCIe edge connector cable.

FMC connector reference numbers

The connector table in the user guide (820977) is offset by one row: the functionality column lags the connector column. The FMC+ connector is J7, not J14 - confirmed by the carrier schematic (150-330724-B1), which routes FMC_GBTCLK0_M2C_DP to J7.D4 and FMC_GBTCLK1_M2C_DP to J7.B20.

FMC power

Rail	Regulator / protection	Limit
+V12P0_FMC	MP5016GQH-L eFuse	ISET = 1.5 A
+V3P3 (shared with HDMI, DP, 2.5G PHY, oscillators, Si53254)	--	7.5 A rail
+V1P2_FMC_ADJ (VADJ)	MPM3632C	2 A

VADJ is 1.2 V as built. The carrier carries a strap (R591) documented as FMC_VADJ=1.8V, and R774 (the 1 mOhm sense resistor in the VADJ path) is marked "to be unmounted to support AD9176 FMC add-in card".

FMC reference clock alternatives

Both FMC transceiver banks have a second reference clock input fed from on-board programmable oscillators, so a mezzanine-supplied clock is optional:

Bank 1B "G" refclk (AY115/AY120) <- CLK_MUX_SI5518_OUT4_SI569_SI549,

selectable between Si5518 OUT4, Si549 (U34) and Si569 (U33), 100 MHz default

Bank 1A "G" refclk (BC107/BC111) <- Si5518 OUT6, mux-selectable to

156.25 / 148.35 / 148.5 / 100 MHz

Bank 1B's GBTCLK0 input additionally passes through a mux (clk_mux_6_sel, EU21) that can substitute the on-board Si549 for the mezzanine clock. All FMC GBTCLK inputs are AC-coupled on the carrier (0.1 uF).

Board revisions

Available as Rev C2 and Rev C3, which differ in board population and power path selection.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*