HES-XCKU11P-DDR4

HES-XCKU11P-DDR4 is an FPGA development board from Aldec, built around the XCKU11P-3FFVE1517E.

• MPN: HES-XCKU11P-DDR4
• Type: FPGA development board
• Vendor: Aldec
• Device: XCKU11P-3FFVE1517E
• Status: active
• Product page: https://www.aldec.com/en/products/emulation/hes_fpga_boards/kintex_ultrascale_plus/hes_xcku11p_ddr4
• Catalog page: https://boards.fpgadeveloper.com/boards/HES-XCKU11P-DDR4
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR4; Size Mb: 8192; Width Bits: 72; Ecc: Yes; Form Factor: sodimm
• Flash:
• Type: QSPI; Size Mb: 64
• EEPROM:
• Interface: I2C; Size Kbits: 64
• Purpose:
• user_data
• Interface: I2C; Size Kbits: 64
• Purpose:
• user_data
• Clocking:
• Programmable: Yes
• PCIe:
• Type: Edge; Gen: 3; Lanes: 16
• Type: Edge; Gen: 4; Lanes: 8
• Networking:
• QSFP Dd: 2
• USB Bridge:
• Connector: Type-A
• Functions:
• jtag
• uart
• Expansion:
• FMC:
• Slot: FMC1; Type: hpc; Vadj Min: 1.0; Vadj Max: 1.8
• Sensors:
• Type: temperature
• User I/O:
• Leds: 4
• Features:
• Power Monitoring: Yes

Device Attributes

Resources

• LUTs: 298,560
• Flip-Flops: 597,120
• Block RAM (36Kb): 600
• UltraRAM: 80
• DSP Slices: 2,928
• MMCMs: 8
• HP I/O Pins: 424
• HD I/O Pins: 96
• Transceivers: 32 (GTH, 16.375 Gb/s max)
• Transceivers: 20 (GTY, 16.5 Gb/s max)

Vivado

• Tool Part: xcku11p-ffve1517-3-e
• ML Standard Support: No

Notes

FMC1 VADJ

FMC1 VADJ is selected manually on the board's DIP switch bank S1, whose printed selection table lists 1.0V, 1.2V, 1.35V, 1.5V and 1.8V. The factory default is 1.8V — all S1 switches ON — which sets both VADJ and the VIOB I/O rail serving the FMC site. VADJ and VIOB are brought out to test points beside the connector, and S1 additionally carries the FMC_POWER_EN / FMC_POWER_ERR functions.

There is no automatic voltage negotiation: the board does not read the mezzanine's IPMI EEPROM, so S1 must be set to a voltage the card accepts before power-up. Selecting the wrong FMC voltage can damage the board or the card.

FMC1 signal coverage

Aldec confirms that every FMC HPC signal is routed at FMC1 except the **DP8 and DP9** transceiver pairs — matching the "8x GTY links" the product page quotes for the site. There is no public pin listing, XDC or constraints file for the connector, so this catalog carries no pin-level routing data for the slot and cannot check FMC mezzanine compatibility against it automatically.

DDR4 SO-DIMM

The SO-DIMM socket is wired 64-bit data plus 8 ECC check bits (72-bit). Boards ship with an 8 GB DDR4-2666 module fitted; other capacities and speeds are available on request. Aldec's published Vivado board files define 1600 and 2133 presets for the interface.

Documentation

Aldec does not publish a user guide or technical specification for this board — the documentation portal requires a login and full documentation is under NDA. This entry is built from the product page, Aldec's published Vivado board files, and details confirmed by Aldec.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*