Genesys-ZU

Genesys-ZU is an FPGA development board from Digilent, built around the XCZU5EV-1SFVC784E.

• MPN: Genesys-ZU
• Type: FPGA development board
• Vendor: Digilent
• Device: XCZU5EV-1SFVC784E
• Status: active
• Price: 1995 USD
• Product page: https://digilent.com/shop/genesys-zu-zynq-ultrascale-mpsoc-development-board/
• Catalog page: https://boards.fpgadeveloper.com/boards/Genesys-ZU
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR4; Size Mb: 4096; Form Factor: sodimm
• Flash:
• Type: QSPI; Size Mb: 32
• PCIe:
• Type: MiniPCIe-Half; Lanes: 1
• Type: MiniPCIe-Full; Lanes: 1; Msata Capable: Yes
• Audio:
• Codec: ADAU1761
• Headphone Jack: 1
• Microphone: 1
• Video:
• HDMI In: 1
• HDMI Out: 1
• Displayport: 1
• Mipi Csi: 2
• Networking:
• SFP Plus: 1
• Ethernet:
• Speed: 1000; Ports: 1
• USB:
• Connector: Type-C; Speed: 3.1; Role: otg
• Connector: Type-A; Speed: 2.0; Role: host; Ports: 2
• USB Bridge:
• Connector: Micro-B
• Functions:
• jtag
• uart
• Expansion:
• Pmod: 4
• Syzygy: 1
• FMC:
• Slot: LPC; Type: lpc; Vadj Min: 1.2; Vadj Max: 1.8
• Storage:
• Microsd: 1
• User I/O:
• Leds: 5
• Pushbuttons: 7
• Dip Switches: 4
• Wireless:
• Wifi: Yes
• Features:
• Programmable Vadj: Yes

Device Attributes

Resources

• LUTs: 117,120
• Flip-Flops: 234,240
• Block RAM (36Kb): 144
• UltraRAM: 64
• DSP Slices: 1,248
• MMCMs: 4
• HP I/O Pins: 159
• HD I/O Pins: 96
• Transceivers: 4 (GTH)

Vivado

• Tool Part: xczu5ev-sfvc784-1-e
• ML Standard Support: Yes

Compatibility

Compatible FMC cards

• RPi Camera FMC (OP068) — compatible, slot LPC, verified
• Ethernet FMC 1.8V (OP031-1V8) — compatible, slot LPC, mechanical
• FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot LPC, mechanical
• Robust Ethernet FMC 1.8V (OP041-1V8) — compatible, slot LPC, mechanical

Notes

VADJ supports 1.2 V / 1.5 V / 1.8 V (discrete values, ±5%). On current boards (Rev. D, Platform MCU firmware 2.0) the Platform MCU (ATmega328PB) reads the FMC mezzanine's IPMI EEPROM at power-up and sets VADJ to the highest commonly supported value — the rail stays disabled (PMCU LED fault) if there is no common value. The PL can override the negotiated voltage via the VADJ_LEVEL1/VADJ_LEVEL0 + VADJ_AUTON pins; on Rev. B boards (firmware 1.0) there is no auto-negotiation and the PL must request a level this way. The VADJ rail is shared by the FMC slot, the SYZYGY/Zmod port, and Pmod JA, so all attached modules must accept the same voltage.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*