EMC2-KU040

EMC2-KU040 is an FPGA development board from Sundance Multiprocessor Technology Ltd., built around the XCKU040-1SFVA784I.

• MPN: EMC2-KU040
• Type: FPGA development board
• Vendor: Sundance Multiprocessor Technology Ltd.
• Device: XCKU040-1SFVA784I
• Status: active
• Price: 3495 GBP
• Product page: https://store.sundance.com/product/emc2-ku040/
• Catalog page: https://boards.fpgadeveloper.com/boards/EMC2-KU040
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR4; Size Mb: 1024; Width Bits: 32
• Type: DDR4; Size Mb: 1024; Width Bits: 32
• Flash:
• Type: QSPI; Size Mb: 64
• Clocking:
• Programmable: Yes
• PCIe:
• Type: PCIe/104; Gen: 2; Lanes: 4
• Video:
• HDMI Out: 1
• Networking:
• Ethernet:
• Speed: 1000; Ports: 1
• Serial:
• Rs232: 1
• Expansion:
• FMC:
• Slot: LPC; Type: lpc; Vadj Min: 1.8; Vadj Max: 3.3
• Storage:
• Sata: 1

Device Attributes

Resources

• LUTs: 242,400
• Flip-Flops: 484,800
• Block RAM (36Kb): 600
• DSP Slices: 1,920
• MMCMs: 10
• HR I/O Pins: 106
• HP I/O Pins: 371
• Transceivers: 8 (GTH, 12.5 Gb/s max)

Vivado

• Tool Part: xcku040-sfva784-1-i
• ML Standard Support: No

Compatibility

Compatible FMC cards

• Ethernet FMC 1.8V (OP031-1V8) — partial, slot LPC, mechanical
• Ethernet FMC 2.5V (OP031-2V5) — partial, slot LPC, mechanical
• Robust Ethernet FMC 1.8V (OP041-1V8) — partial, slot LPC, mechanical
• Robust Ethernet FMC 2.5V (OP041-2V5) — partial, slot LPC, mechanical

Notes

FMC VADJ is jumper-selectable between 1.8 V, 2.5 V and 3.3 V (discrete values): the FMC connector's VADJ pins are tied to the SoM's FPGA I/O bank rail (VCCIO), and jumper JP8 (with JP8A) selects that rail's voltage — position 1-2 for 3.3 V, 2-3 for 1.8 V, 2-JP8A for 2.5 V. Set the jumper before power-on; the board does not read the FMC IPMI EEPROM. Caution: HP FPGA banks only support up to 1.8 V — the safe setting depends on the fitted SoM, and Sundance may ship the board with only the 1.8 V selection populated.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*