Agilex 5 E-Series 065B Premium

Agilex 5 E-Series 065B Premium is an FPGA development board from Altera, built around the A5ED065BB32AE4S.

• MPN: DK-A5E065BB32AEA
• Type: FPGA development board
• Vendor: Altera
• Device: A5ED065BB32AE4S
• Status: active
• Price: 3125 USD
• Product page: https://www.altera.com/products/devkit/po-3284/agilex-5-fpga-e-series-065b-premium-development-kit
• Catalog page: https://boards.fpgadeveloper.com/boards/DK-A5E065BB32AEA
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR4; Size Mb: 8192; Width Bits: 40; Ecc: Yes
• Type: DDR4; Size Mb: 8192; Width Bits: 40; Ecc: Yes
• Type: LPDDR4; Size Mb: 4096; Width Bits: 32
• Flash:
• Type: QSPI; Size Mb: 256
• Networking:
• QSFP Plus: 2
• SFP Plus: 2
• Ethernet:
• Speed: 1000; Ports: 2
• Speed: 2500; Ports: 1
• Video:
• Mipi Csi: 1
• High Speed I/O:
• Form: SMA; Count: 2; Max Rate Gbps: 17.16; Transceiver: GTS
• Expansion:
• FMC:
• Slot: J34; Type: fmcp; Vadj Min: 1.2; Vadj Max: 1.3
• Storage:
• Microsd: 1
• USB Bridge:
• Connector: Micro-B
• Functions:
• jtag
• User I/O:
• Leds: 4
• Pushbuttons: 4
• Dip Switches: 4
• Clocking:
• Programmable: Yes
• Features:
• Power Monitoring: Yes

Compatibility

Compatible FMC cards

• 2x QSFP28 FMC (OP120) — compatible, slot J34, mechanical
• Ethernet FMC Max (OP080) — compatible, slot J34, mechanical
• FPGA Drive FMC Gen4 (OP063) — compatible, slot J34, mechanical
• M.2 M-key Stack FMC (OP073) — compatible, slot J34, mechanical
• MCIO PCIe FMC (OP103) — compatible, slot J34, mechanical
• Quad SFP28 FMC (OP081) — compatible, slot J34, mechanical
• RPi Camera FMC (OP068) — compatible, slot J34, mechanical

Notes

Transceiver bank map

All 24 GTS channels (6 banks x 4) are committed:

The FMC+ site therefore presents two whole quads, each with its own mezzanine-supplied reference clock in the same bank as its lanes.

Documentation error: Table 21 (FMC Connector J34) in the user guide (814550) lists the I/O Bank column with 4B and 4C swapped relative to both the prose in section A.8.4 and the production schematic (150-0330713-A3). The schematic is authoritative: FMC_RX0_P -> GTSR4C_RX_CH0P and FMC_GBTCLK0_M2C_P -> REFCLK_GTSR4C_CH1P (both bank 4C); FMC_RX4_P and FMC_GBTCLK1_M2C_P are both in bank 4B.

FMC power

VADJ is adjustable between 1.2 V and 1.3 V only. The user guide states the kit "does not support FMC cards that are not compliant with Agilex 5 FPGA 1.2-V/1.3-V I/O standard".

FMC reference clocks

Each FMC transceiver bank also has a second reference clock input driven from an on-board programmable oscillator, so a mezzanine clock is not mandatory:

• Bank 4B REFCLK_GTSR4B_RX <- FMC_VCXO_REFCLK (Si569 VCXO X5, 148.35 MHz

default, switchable to 148.5 MHz, LVDS 2.5 V)

• Bank 4C REFCLK_GTSR4C_RX <- FMC_PROG_REFCLK (Si548 XO X6, 135 MHz

default, LVDS 2.5 V)

The GBTCLK0/1_M2C inputs are AC-coupled on the carrier (0.22 uF).

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*