AC701
AC701 is an FPGA development board from AMD Xilinx, built around the XC7A200T-2FBG676C.
- MPN: AC701
- Type: FPGA development board
- Vendor: AMD Xilinx
- Device: XC7A200T-2FBG676C
- Status: active
- Price: 1678 USD
- Product page: https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/ek-a7-ac701-g.html
- Catalog page: https://boards.fpgadeveloper.com/boards/AC701
- Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json
Specifications
- Memory:
- Type: DDR3; Size Mb: 1024; Form Factor: sodimm
- Flash:
- Type: QSPI; Size Mb: 32
- Clocking:
- Programmable: Yes
- Sma Clock In: 2
- PCIe:
- Type: Edge; Gen: 2; Lanes: 4
- High Speed I/O:
- Form: SMA; Lanes: 1
- Video:
- HDMI Out: 1
- Display:
- Character Lcd: 2x16
- Networking:
- SFP Plus: 1
- Ethernet:
- Speed: 1000; Ports: 1
- USB Bridge:
- Connector: Micro-B
- Functions:
- jtag
- Connector: Mini-B
- Functions:
- uart
- Expansion:
- Pmod: 1
- Xadc Header: 1
- FMC:
- Slot: HPC; Type: hpc; Vadj Min: 1.8; Vadj Max: 3.3
- Storage:
- SD: 1
- User I/O:
- Leds: 4
- Pushbuttons: 5
- Dip Switches: 4
- Rotary Encoders: 1
- Features:
- Power Monitoring: Yes
Device Attributes
Resources
- LUTs: 134,600
- Flip-Flops: 269,200
- Block RAM (36Kb): 365
- DSP Slices: 740
- MMCMs: 10
- HR I/O Pins: 400
- Transceivers: 8 (GTP, 6.25 Gb/s max)
Vivado
- Tool Part: xc7a200tfbg676-2
- ML Standard Support: Yes
Compatibility
Compatible FMC cards
- Ethernet FMC 2.5V (OP031-2V5) — compatible, slot HPC, verified
- Robust Ethernet FMC 2.5V (OP041-2V5) — compatible, slot HPC, verified
- Ethernet FMC 1.8V (OP031-1V8) — compatible, slot HPC, mechanical
- FL9627 4-Channel High-Speed AD Module (FL9627) — compatible, slot HPC, mechanical
- Robust Ethernet FMC 1.8V (OP041-1V8) — compatible, slot HPC, mechanical
- 2x QSFP28 FMC (OP120) — partial, slot HPC, mechanical
- Ethernet FMC Max (OP080) — partial, slot HPC, mechanical
- FPGA Drive FMC Gen4 (OP063) — partial, slot HPC, mechanical
- M.2 M-key Stack FMC (OP073) — partial, slot HPC, mechanical
- Quad SFP28 FMC (OP081) — partial, slot HPC, mechanical
Notes
Configuration
FPGA configuration is determined by DIP switch SW1.
| Config mode | 1 | 2 | 3 |
|---|
| JTAG | 1 | X | 1 |
| Master SPI | 0 | X | 1 |
Notes:
1. Switch 2 is not used 2. X = don't care 3. 0 = OFF position 4. 1 = ON position
--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*