Agilex 7 FPGA Starter Kit

Agilex 7 FPGA Starter Kit is an FPGA development board from Terasic, built around the AGFB027R24C2E2VC.

• MPN: A7SK
• Type: FPGA development board
• Vendor: Terasic
• Device: AGFB027R24C2E2VC
• Status: active
• Price: 5491 USD
• Product page: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=142&No=1295
• Catalog page: https://boards.fpgadeveloper.com/boards/A7SK
• Structured data (JSON): https://boards.fpgadeveloper.com/data/boards.json

Specifications

• Memory:
• Type: DDR4; Size Mb: 8192; Width Bits: 72; Ecc: Yes; Form Factor: sodimm
• Type: DDR4; Size Mb: 8192; Width Bits: 72; Ecc: Yes
• Sensors:
• Type: temperature
• Clocking:
• Programmable: Yes
• PCIe:
• Type: Edge; Gen: 4; Lanes: 8
• Video:
• HDMI Out: 1
• Networking:
• Qsfp28: 1
• Ethernet:
• Speed: 1000; Ports: 1
• USB Bridge:
• Connector: Micro-B
• Functions:
• jtag
• uart
• Expansion:
• GPIO Header: 1
• FMC:
• Slot: FMCP; Type: fmcp; Vadj Min: 1.2; Vadj Max: 1.2
• Storage:
• Microsd: 1
• User I/O:
• Leds: 2
• Pushbuttons: 2
• Dip Switches: 2
• Features:
• Power Monitoring: Yes

Compatibility

Compatible FMC cards

• 2x QSFP28 FMC (OP120) — compatible, slot FMCP, mechanical
• Ethernet FMC Max (OP080) — compatible, slot FMCP, mechanical
• FPGA Drive FMC Gen4 (OP063) — compatible, slot FMCP, mechanical
• M.2 M-key Stack FMC (OP073) — compatible, slot FMCP, mechanical
• MCIO PCIe FMC (OP103) — compatible, slot FMCP, mechanical
• Quad SFP28 FMC (OP081) — compatible, slot FMCP, mechanical
• RPi Camera FMC (OP068) — compatible, slot FMCP, mechanical

Notes

The FPGA-side DDR4 SO-DIMM socket (DDR4-A) is shared with the HPS: it can be driven by the HPS EMIF or, when the HPS EMIF is unused, by the FPGA fabric. The on-board 8 GB DDR4-B bank is always FPGA-fabric side. The socket accepts up to a 16 GB single-rank SO-DIMM; the kit ships with an 8 GB ECC module.

Configuration mode is set by the two MSEL slide switches:

Other default settings worth knowing before first power-on:

• PCIe presence detect — a DIP switch selects x1 / x4 / x8 presence detect; the default is x8 detect enabled, x1 and x4 disabled.
• JTAG bypass — both positions of the JTAG bypass switch default to ON, which keeps the HPS and the FMC+ connector *out* of the board JTAG chain. Switching a position OFF without a JTAG device present on that branch breaks the chain and Quartus will no longer detect the FPGA.
• Force external power — this switch defaults to ON, so the 2x4 12 V auxiliary power connector must be attached even when the card sits in a host PCIe slot, otherwise the board will not power up.
• FMC_VCCIO select header (JP1) — a 3-pin jumper sets VCCIO_FMCP_HAB, the VCCIO of the FPGA bank serving the FMC+ HA/HB pins and CLK1_M2C, to 1.2 V (default) or 1.5 V.

This is a host-side bank rail only — it does not change VADJ: the FMC+ connector's VADJ rail is fixed at 1.2 V (4 A max), and the FMC+ LA-bank I/O is fixed at 1.2 V, so a mezzanine always sees 1.2 V VADJ regardless of the jumper. The user manual calls this header JP1 in one section and JP2 / JP3 in two others; the board silkscreen reads JP1.

The factory SoC boot flow is FPGA-configuration-first: the SDM loads its firmware, the FPGA image and the HPS first-stage boot loader from the QSPI flash, then the second-stage boot loader, kernel and root filesystem come from the microSD card.

Earlier board revisions shipped earlier steppings of the same device — AGFB027R24C2E2V and AGFB027R24C2E2VB, both now EOL. Current boards carry AGFB027R24C2E2VC.

--- *Machine-readable catalog entry from https://boards.fpgadeveloper.com. Full dataset: https://boards.fpgadeveloper.com/llms.txt*